In recent years, as liquid crystal panels, etc. have been made larger in size and higher in definition, liquid crystal driving semiconductor integrated circuits have evolved to have a larger number of liquid crystal driving output terminals and to output more levels of gray-scale voltage through the output terminals. For example, some of the currently mainstream liquid crystal driving semiconductor integrated circuits each include approximately 500 output terminals through each of which 256 levels of gray-scale voltage can be outputted. Furthermore, liquid crystal driving semiconductor integrated circuits each including 1,000 or more output terminals are currently under development. Further, as liquid crystal panels are enabled to show more colors, liquid crystal driving semiconductor integrated circuits capable of outputting 1,024 levels of gray-scale voltage are also under development.
The configuration of a conventional liquid crystal driving semiconductor integrated circuit is described below with reference to FIG. 53. FIG. 53 is a block diagram showing the configuration of a conventional liquid crystal driving semiconductor integrated circuit.
A liquid crystal driving semiconductor integrated circuit 101 of FIG. 53 can output m levels of gray-scale voltage through each of the n liquid crystal driving signal output terminals. First, the configuration of the liquid crystal driving semiconductor integrated circuit 101 is described. The liquid crystal driving semiconductor integrated circuit 101 externally includes: a clock input terminal 102; a gray-scale data input terminal 103 including a plurality of signal input terminals; a LOAD signal input terminal 104; and reference supply terminals, namely a V0 terminal 105, a V1 terminal 106, a V2 terminal 107, a V3 terminal 108, and a V4 terminal 109. The liquid crystal driving semiconductor integrated circuit 101 further includes n liquid crystal driving signal output terminals 111-1 to 111-n (such liquid crystal driving signal output terminals being hereinafter referred to as “signal output terminals”; the liquid crystal driving signal output terminals 111-1 to 111-n being sometimes referred to collectively as “signal output terminals 111”). Further, the liquid crystal driving semiconductor integrated circuit 101 includes a reference supply correction circuit 121, pointer shift-register circuits 123, a latch circuit section 124, hold circuits 125, D/A converter (digital-analog converter; hereinafter referred to as “DAC”) circuits 126, and output buffers 127. Further, the pointer shift-register circuits 123 are constituted by n shift register circuits 123-1 to 123-n. Furthermore, the latch circuit section 124 is constituted by n latch circuits 124-1 to 124-n, and the hold circuits 125 are constituted by n hold circuits 125-1 to 125-n. Further, the DAC circuits 126 are constituted by n DAC circuits 126-1 to 126-n. In addition, the output buffers 127 are constituted by n output buffers 127-1 to 127-n each constituted by an operational amplifier.
Next, the operation of the liquid crystal driving semiconductor integrated circuit 101 is described. The pointer shift-register circuits 123 select the first to nth latch circuits 124-1 to 124-n in sequence in accordance with a clock input signal inputted through the clock input terminal 102. When selected by the pointer shift-register circuits 123, the latch circuits 124 store therein gray-scale data inputted through the gray-scale data input terminal 103, respectively. It should be noted that the gray-scale data correspond to each separate latch circuit 124; in other words, the gray-scale data are data, synchronized with the clock input signal, which correspond to each separate signal output terminal 111. Further, the latch circuits 124-1 to 124-n send, to the hold circuits respectively connected thereto, different values of gray-scale data corresponding to each separate signal output terminal 111. Upon receiving the gray-scale data, the hold circuits 125 send the gray-scale data as digital data to the DAC circuits 126-1 to 126-n, respectively, in accordance with a data LOAD signal.
At this point, the DAC circuits 126-1 to 126-n each select a voltage from the m levels of gray-scale voltage in accordance with the gray-scale data sent from the hold circuits 125, and then send the voltages to the output buffers 127-1 to 127-n, respectively. It should be noted that each of the DAC circuits 126 can output the m levels of gray-scale voltage, depending on voltages inputted through the reference supply terminals, namely the V0 to V4 terminals 105 to 109. Next, the output buffers 127 buffer the gray-scale voltages sent from the DAC circuits 126, and then send the gray-scale voltages as liquid crystal driving signals to the signal output terminals 111-1 to 111-n, respectively.
Next, a specific example of a configuration of shift registers 123, latch circuits 124, and hold circuits 125 is described with reference to FIG. 54.
FIG. 54 shows the configuration of a liquid crystal driving semiconductor integrated circuit 101 including eighteen liquid crystal driving signal output terminals OUT1 to OUT18. The liquid crystal driving semiconductor integrated circuit 101 includes: pointer shift registers DF_1 to DF_18 (hereinafter sometimes referred to collectively as “pointer shift registers DF”), which correspond to the point shift-register circuits 123 of FIG. 53; latch circuits DLA_1 to DLA_18 (hereinafter sometimes referred to collectively as “latch circuits DLA”), which correspond to the latch circuits 124 of FIG. 53; hold circuits DLB_1 to DLB_18 (hereinafter sometimes referred to collectively as “hold circuits DLB”), which correspond to the holds circuits 125 of FIG. 53; and output circuits 11_1 to 11_18, which correspond to the DAC circuits 126 and output buffers 127 of FIG. 53. The liquid crystal driving semiconductor integrated circuit 101 receives an operation start signal (SP signal) indicative of the timing of start of the pointer shift registers through a start pulse signal line (SP signal line) and receives an operation clock signal through a clock signal line (CLK signal line), and these signals correspond to the shift clock input signal of FIG. 53. The liquid crystal driving semiconductor integrated circuit 101 receives gray-scale data through a DATA signal line, and the data correspond to the gray-scale data of FIG. 53. The liquid crystal driving semiconductor integrated circuit 101 receives a data LOAD signal through an LS signal line, and this signal correspond to the data LOAD signal of FIG. 53.
As shown in FIG. 54, the pointer shift registers DF are each constituted by a D flip-flop, and the latch circuits DLA and the hold circuits DLB are each constituted by a D latch. Furthermore, the liquid crystal driving semiconductor integrated circuit 101 includes as many pointer shift registers DF, latch circuits DLA, and hold circuits DLB as the liquid crystal driving signal output terminals OUT.
FIG. 55 is a timing chart showing the operation of the pointer shift register circuits 123. Among the shift register circuits 123, first, the pointer shift register DF_1 receives a “H” SP signal indicative of the start of operation of the integrated circuit 101 through its input section D. The pointer shift register DF_1 loads the value “H” of the SP signal in response to a rise in the CLK signal, and then outputs a “H” selection signal through its output section . As shown in FIG. 55, at the next rising edge of the CLK signal, the SP signal is “L” and, accordingly, the selection signal from the pointer shift register DF_1 through its output section  becomes “L”, too. It should be noted, in FIG. 55, that (DF_1) to (DF_18) denote selection signals from the pointer shift registers DF_1 to DF_18, respectively.
The pointer shift registers DF_1 to DF_18 constitute a shift register by having their output sections  connected to the input sections D of the next pointer shift registers, respectively. That is, before the selection signal  (DF_1) from the pointer shift register DF_1 becomes “L”, the pointer shift register DF_2 outputs a “H” selection signal (DF_2) in response to a rise in the CLK signal. After that, the selection signal (DF_1) becomes “L”. This operation process is repeated for each of the pointer shift registers DF_2 to DF_18. As shown in FIG. 55, in synchronization with falls rises in the CLK signal, the pointer shift registers DF send the selection signals in sequence to the latch circuits DLA connected to the output sections  of the pointer shift registers DF, respectively.
As described above, as many shift register circuits 123, latch circuits 124, hold circuits 125, DAC circuits 126, and output buffers 127 are required as the liquid crystal driving signal output terminals 111. In the case of 1,000 liquid crystal driving signal output terminals 111, 1,000 latch circuits 124, 1,000 hold circuits 125, 1,000 DAC circuits 126, and 1,000 output buffers 127 are required accordingly.
The configuration of another conventional liquid crystal driving semiconductor integrated circuit is described below with reference to FIG. 56. FIG. 56 is a block diagram showing the configuration of another conventional liquid crystal driving semiconductor integrated circuit. A liquid crystal driving semiconductor integrated circuit 101′ of FIG. 56 differs from the liquid crystal driving semiconductor integrated circuit 101 of FIG. 53 only in the configuration of a pointer circuit 123′. In the following, therefore, only the configuration of the pointer circuit 123′ is described, and the same members as those shown in FIG. 53 are given the same reference numerals and, as such, are not described.
The pointer circuit 123′ is constituted by a counter and a decoder. Furthermore, the latch circuits 124 are constituted by n latch circuits 124-1 to 124-n, and the hold circuits 125 are constituted by n hold circuits 125-1 to 125-n. Further, the DAC circuits 126 are constituted by n DAC circuits 126-1 to 126-n. In addition, the output buffers 127 are constituted by n output buffers 127-1 to 127-n each constituted by an operational amplifier.
Next, the operation of the liquid crystal driving semiconductor integrated circuit 101′ is described. The pointer circuit 123′ selects the first to nth latch circuits 124-1 to 124-n in sequence in accordance with counting of a clock input signal inputted through the clock input terminal 102. When selected by the pointer circuit 123′, the latch circuits 124 store therein gray-scale data inputted through the gray-scale data input terminal 103. It should be noted that the gray-scale data correspond to each separate latch circuit 124; in other words, the gray-scale data are data, synchronized with the clock input signal, which correspond to each separate signal output terminal 111. Further, the latch circuits 124-1 to 124-n send, to the hold circuits respectively connected thereto, different values of gray-scale data corresponding to each separate signal output terminal 111. Upon receiving the gray-scale data, the hold circuits 125 send the gray-scale data as digital data to the DAC circuits 126-1 to 126-n, respectively, in accordance with a data LOAD signal.
At this point, the DAC circuits 126-1 to 126-n each select a voltage from the m levels of gray-scale voltage in accordance with the gray-scale data sent from the hold circuits 125, and then send the voltages to the output buffers 127-1 to 127-n, respectively. It should be noted that each of the DAC circuits 126 can output the m levels of gray-scale voltage, depending on voltages inputted through the reference supply terminals, namely the V0 to V4 terminals 105 to 109. Next, the output buffers 127 buffer the gray-scale voltages sent from the DAC circuits 126, and then send the gray-scale voltages as liquid crystal driving signals to the signal output terminals 111-1 to 111-n, respectively.
Next, a specific example of a configuration of a liquid crystal driving semiconductor integrated circuit 101′ including a pointer circuit 123′, latch circuits 124, and hold circuits 125 is described with reference to FIG. 57.
FIG. 57 shows eighteen liquid crystal driving signal output terminals OUT1 to OUT18 for illustrative purposes. The latch circuits DLA_1 to DLA_18 (hereinafter sometimes referred to collectively as “latch circuits-DLA”) correspond to the latch circuits 124 of FIG. 56. The hold circuits DLB_1 to DLB_18 (hereinafter sometimes referred to collectively as “hold circuits DLB”) correspond to the hold circuits 125 of FIG. 56. The output circuits 11_1 to 11_18 correspond to the DAC circuits 126 and output buffers 127 of FIG. 56.
Further, a start signal inputted through a SP signal line and indicating the timing of start of the counter and a clock signal inputted through a CLK signal line correspond to the shift clock input signal of FIG. 56. A data LOAD signal inputted through an LS signal, line corresponds to the data LOAD signal of FIG. 56.
FIG. 58 shows the configuration of the pointer circuit 123′. The pointer circuit 123′ is constituted by a set/reset circuit, a counter, and a decoder.
Upon receiving an operation start signal (SP signal) through a start pulse signal line (SP signal line), a clock signal (CLK signal) through a clock signal line (CLK signal line), and a selection signal (SEL signal) through a selection signal line SEL18 to be described later, the set/reset circuit generates an operation clock signal (CLKB signal) for the counter 123_2 and outputs it through a counter clock signal line (CLKB signal line).
The counter is constituted by five D flip-flops DF_1 to DF_5 (hereinafter sometimes referred to collectively as “DFFs”). The counter 123_2 receives the CLKB signal and the SP signal, and then generates D1 to D5 and D1B to D5B in accordance with C1 to C5 sent from the DFFs, respectively.
The decoder performs arithmetical operations according to logical expressions shown in FIG. 58 to generate selection signals to be outputted to selection signal lines SEL0 to SEL17 (SEL signal lines) of FIG. 57. It should be noted that the decoder is not particularly limited in specific configuration, so long as it can perform logical operations as shown in FIG. 58.
FIG. 59 is a timing chart showing the operation of the pointer circuit 123′. In the pointer circuit 123′, the input of the operation clock signal to the counter 123_2 through the CLKB signal line is started when the SP signal becomes “H”. The CLKB signal is an inversion signal of the CLK signal.
The counter 123_2 counts up at a falling edge of the operation clock signal inputted through the CLKB signal line. However, the DFFs are reset during a period of time when the operation start signal (SP signal) inputted through the start pulse signal line (SP signal line) is “H”. Therefore, C1 to C5 outputted from the DFFs are all “L”. During this period, the decoder 123_3 outputs a “H” selection signal to the selection signal line SEL0. After the SP signal becomes “L”, the counter 123_2 counts up at a falling edge of the operation clock signal (CLKB signal) inputted through the counter clock signal line (CLKB signal line). Accordingly, C1 becomes “H”, whereby the decoder 123_3 comes to output a “H” selection signal to the selection signal line SEL1. Hereafter, every time the counter 123_2 counts up, the decoder 123_3 comes to output “H” selection signals to the selection signal lines SEL2 to SEL17 in sequence. When the decoder 123_3 comes to output a “H” selection signal to the selection signal line SEL18, the set/reset circuit 123_1 is reset to stop receiving the operation clock signal through the CLKB signal line. Accordingly, the counter 123_2 stops, too.
Since display devices such as liquid crystal panels have been made larger in size and higher in definition in recent years as mentioned above, a full-specification high definition television (HDTV) includes 1,920 data lines. Because a display driving semiconductor integrated circuit needs to supply R, G, and B gray-scale voltage signals for each data line, the display driving semiconductor integrated circuit needs to include 5,760 (=1,920×3 [R, G, and B]) liquid crystal driving signal output terminals. In this case, the number of display driving semiconductor integrated circuits required is 8, assuming that each of the display driving semiconductor integrated circuits has 720 liquid crystal driving signal output terminals.
In general, display driving semiconductor integrated circuits are tested as wafers, tested for shipping after packaging, and tested for displays after being mounted on liquid crystal panels. Furthermore, those semiconductor integrated circuits which may show initial defects are eliminated by screening tests such as burn-in tests and stress tests. Therefore, no display devices that are shipped to the market include display driving semiconductor integrated circuits which cause defective displays. However, a defective display occurs infrequently during use of a display device due to an extremely small defect or extraneous matter that was not judged as a defect during a pre-shipment test or screening test. For example, even if the probability of occurrence of a defective display in one data line of a display driving semiconductor integrated circuit after shipment is 0.01 ppm (one part per 100 million), the probability of occurrence of a defective display in a full-specification HDTV having 5,760 data lines is 57.6 ppm (57.6 parts per million). This means that one out of approximately 17,361 full-specification HDTVs shows a defective display. The larger in size and higher in definition HDTVs become, the higher the probability of occurrence of a defective display becomes.
In the case of occurrence of such a defective display, it is necessary to recall the display devices and repair the display driving semiconductor integrated circuits. It surely takes substantial cost to swiftly recall the display devices and repair them and, what is more, the display devices' brand image is damaged.
Disclosed in this regard is a conventional technique for avoiding a failure in a display driving semiconductor integrated circuit by providing the display driving semiconductor integrated circuit with a spare circuit that is used to replace a defective circuit and switching from the defective circuit to the spare circuit.
Specifically, Patent Literature 1 discloses a method for avoiding a defective display due to a defective shift register by making a display driving semiconductor integrated circuit have shift registers each provided with a spare circuit parallel thereto, self-inspecting the shift registers, and selecting a nondefective one of the circuits parallel to each other in accordance with a result of the detection. Furthermore, Patent Literature 2 discloses a method for switching from a defective DAC circuit to a spare DAC circuit by providing a selector at each of the input and output of each DAC circuit and switching the selector in accordance with information stored in a RAM and indicating the location of a defective DAC circuit.